GCS PDKs provide in-house validated device models and comprehensive layout libraries to support your designs. Available for use in Keysight ADS and/or Cadence Microwave Office (MWO), our PDKs enable accurate circuit and EM-level simulation, as well as physical verification through Design Rule Checking (DRC) and Layout vs. Schematic (LVS) validations.
Device Models
- Nonlinear active devices
- Passive component devices
- Statistical Variation parameters (Corner & Monte Carlo)
- Advanced Thermal and Electro-thermal physics models
Schematic Symbols and Libraries
- Fully parameterized schematic symbols
- Technology-specific manufacturing component libraries
Layout PCells and Libraries
- Parameterized Cells (PCells for transistors, inductors, MIM capacitors, and resistors)
- Transmission Line and RF Interconnect PCells
- Standard foundry layout cells (Pads, Backside Vias, etc.)
- Accurate Layer definitions and standardized color maps
Technology & Process Files
- EM Stackup multi-layer setup files
- Substrate and GDS layer cross-maps
- Targeted foundry process rule options
Verification Decks
- DRC (Design Rule Check) validation modules
- LVS (Layout vs. Schematic) geometry cross-checking
